The present invention relates to circuits and methods for reducing electrical stress on a transistor.
Integrated circuits are typically built using transistors, such as metal oxide semiconductor (MOS) transistors, for example. Over the years, the number of transistors on an integrated circuit has increased significantly. The increase in transistor density has led to many benefits and challenges. For example, as devices are made smaller, the susceptibility of such devices to electrical stress and breakdown increases.
FIG. 1 illustrates a structure of a traditional MOS transistor 100. MOS transistor 100 includes p-type region 105 having a portion acting as a channel, an n+ type source region 103, and an n+ drain region 104. Dielectric layer 102 covers portions of n+ type source region 103 and n+ type drain region 104 and covers the portion of the p-type region 105 acting as a channel. Above dielectric layer 102 is a poly-silicon layer 101. As the dimensions of transistor 100 are reduced, the dimensions of the regions specified above are also reduced. In particular, as the transistor size is reduced, the dielectric layer 102 may be manufactured thinner. However, the thinner dielectric may also make the transistor gate more vulnerable to gate dielectric stress when voltages are applied across the gate and source terminals. Such stress may cause damage to the dielectric and damage the device.
Therefore, it would be desirable to reduce electrical stress on a transistor. The present invention solves these and other problems by providing circuits and methods for reducing stress on a transistor.